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FEDL7020-01
Semiconductor 1 ML7020
1200 bps MODEM for ACR
This version: Feb. 2000
GENERAL DESCRIPTION
The ML7020 is a 1200 bps modem LSI developed for ACR (Automatic Cost Routing). The functions incorporated are those of a 1200 bps FSK modem conforming to ITU-T Recommendations V.23, DTMF signal generation and detection, call progress tone (CPT) generation and detection. Each functional block can be controlled via a 4-bit processor interface. In addition to ACR, this LSI is ideal for other communications such as remote control systems, etc. * Single 5 V power supply operation (VDD: 4.5 to 5.5 V) * Low power consumption: During operation: 5 mA typ. During the power down mode: 7 A typ. * Built-in 1200 bps modem conforming to ITU-T V.23 recommendations * Built-in DTMF signal generator with a switchable 6-dB attenuator * Built-in DTMF detector (the input can be selected from either the line or the terminal) * Built-in call progress tone generator. The output frequency can be selected from 400 Hz and 800 Hz. * Built-in call progress tone detector * Three analog input systems (switchable) * Analog output for the line is of the differential type and can drive a 600 line transformer. * Analog output for the terminal is of the single-ended type and can drive a 1.2 k load. * Built-in switch for selecting the 600 termination * 4-Bit processor interface * Built-in oscillator circuit for a 3.579545 MHz crystal * Package: 32-Pin plastic SSOP (SSOP32-P-430-1.00-K) (Product name: ML7020MB)
FEATURES
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BLOCK DIAGRAM
Input Amplifier 1 TI- TI+ TIO Input Amplifier 2 LI1- LI1+ LI1O Input Amplifier 3 LI2- SW2 Modem Reception RD CPT Detection DETB
SW1 DTMF Reception SP
LI2O Output Amplifier 1 TO 1.2 k Output Amplifier 2 LO- LO+ -1 1.2 k +1 Output Amplifier 3 SWI SW3 SGO SGC SG Oscillator Circuit Modem Transmission PostLPF SW5 DTMF Transmission XD SW4 CPT Transmission
ATT
X1 X2 CLKO
MCU I/F
* CPT: Call progress tone * The state shown of each switch is that when the register is set to "0".
D3 to D0
WRB
CSB
RDB
A1, A0
VDD GND
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PIN CONFIGURATION (TOP VIEW)
32-Pin plastic SSOP
VDD TIO TI- TI+ LI1O LI1- LI1+ SWI SGO LI2O LI2- TO LO+ LO- SGC GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
SP DETB RD XD X1 X2 CLKO D3 D2 D1 D0 A1 A0 WRB RDB CSB
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PIN DESCRIPTIONS
Pin No. 1 2 Symbol VDD TIO O I/O Power supply pin. Description Connect a +5 V power supply to this pin. The output pin of the input amplifier 1. See Figure 1. For the sake of noise reduction, connect a capacitor between this pin and TI- (3) so as to attenuate high frequency components above 10 kHz. The inverting input pin for the input amplifier 1. When the input amplifier 1 is not used, connect pin TIO (2) to pin TI- (3), and connect pin TI+ (4) to pin SGO. The non-inverting input pin for the input amplifier 1. The output pin for the input amplifier 2. See Figure 1. For the sake of noise reduction, connect a capacitor between this pin and LI1- (6) so as to attenuate high frequency components above 10 kHz. The inverting input pin for the input amplifier 2. When the input amplifier 2 is not used, connect pin LI1O (5) and LI1- (6), and connect pin LI+ (7) to pin SGO. The non-inverting input pin for the input amplifier 2. The input pin for SW3. to be made ON. This pin is connected internally to SGO (9) when SW3 is A voltage of about VDD/2 is
3 4 5
TI- TI+ LI1O
I I O
6 7 8 9
LI1- LI1+ SWI SGO
I I I O
The signal ground output pin for external circuits. output from this pin.
10
LI2O
O
The output pin for the input amplifier 3. See Figure 1. For the sake of noise reduction, connect a capacitor between this pin and LI2- (10) so as to attenuate high frequency components above 10 kHz. The inverting input pin for the input amplifier 3. When the input amplifier 3 is not used, connect pin LI2O (10) and LI2- (11). The output pin of the output amplifier 1. Can drive a load of 1.2 k or more. The non-inverting output pin for the output amplifier 2. of connecting a peripheral circuit. The inverting output pin of the output amplifier 2. connecting a peripheral circuit. The signal ground output pin for internal circuits. output from this pin. The ground pin for the LSI. See Figure 2 for details
11 12 13 14
LI2- TO LO+ LO-
I O O O
See Figure 2 for details of A voltage of about VDD/2 is
15 16 17
SGC GND CSB
O
Connect a 1 F capacitor between SGC (15) and GND (16). Connect a 0 V input to this pin. The chip select pin for the processor interface. I Reading and writing are possible when this input is "0". Reading and writing are disabled when this input is "1". The read control pin for the processor interface. Data can be read from the LSI when this pin is "0". The write control pin for the processor interface. Data is written into this LSI at the rising edge of the WR signal. The address input pin A0 for the processor interface.
18 19 20
RDB WRB A0
I I I
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Pin No. 21 22 23 24 25 26 27 28
Symbol A1 D0 D1 D2 D3 CLKOUT X2 X1
I/O I
Description The address input pin A1 for the processor interface.
IO The data input/output pin D0 for the processor interface. IO The data input/output pin D1 for the processor interface. IO The data input/output pin D2 for the processor interface. IO The data input/output pin D3 for the processor interface. O O I The 3.579545 MHz oscillator circuit output pin. The pins for connecting a 3.579545 MHz crystal. The capacitors and the feedback resistor are internally connected to these pins. When inputting an external clock, connect the input to the X1 pin via a 1000 pF capacitor and leave the pin X2 open. The modem transmit data input pin. The "1" level corresponds to the mark data and the "0" level corresponds to the space data. The modem receive data output pin. The mark and space data are the same as for XD. A mark is output when no carrier is detected. The pin for outputting the carrier detect signal of the modem or the call progress tone detector output. The detection result corresponding to the respective operating mode is output from this pin. A "0" indicates detection and a "1" indicates non-detection. The DTMF reception detection output pin. A "0" indicates detection and a "1" indicates non-detection.
29
XD
I
30
RD
O
31
DETB
O
32
SP
O
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TIO R1 Terminal C1 R2 Input amplifier 1 TI- TI+ SGO LI1O R3 Line 1 C2 R4 Input amplifier 2 LI1- Example: The cutoff frequency is fc = 10 kHz, when R3 = R4 = 30 k (gain = 1), and C2 is 500 pF VREF Example: The cutoff frequency is fc = 10 kHz, when R1 = R2 = 30 k (gain = 1), and C1 is 500 pF
LI2O R5 Line 2 C3 R6 Input amplifier 3 LI2-
Example: The cutoff frequency is fc = 10 kHz, when R5 = R6 = 30 k (gain = 1), and C3 is 500 pF
Figure 1
Input amplifier 1 to 3 interface
Output amplifier 2
600 LO- (-10.0 dBm) 0.022 F (-10.0 dBm) LO+ Output amplifier 3
600 : 600
-10.0 dBm
(When the transformer loss is 0 dB)
Figure 2
Output amplifier 2, 3 interface example
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ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Permissible power dissipation Output short circuit current Analog input voltage Digital input voltage Storage temperature range Symbol VDD PD ISHT VAIN VDIN Tstg Condition -- -- Shorted to VDD or ground. -- -- -- Rating -0.3 to +7.0 to 130 to 60 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -55 to +150 Unit V mW mA V V C
RECOMMENDED OPERATING CONDITIONS
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter Power supply voltage Operating temperature range High level input voltage Low level input voltage Digital input rise time Digital input fall time Digital output load Bypass capacitor for SGC Bypass capacitor for VDD Oscillating frequency Frequency deviation Crystal Temperature characteristics Equivalent series resistor Production load capacitance Input clock frequency deviation Input clock duty ratio Symbol VDD Ta VIH VIL tir tif CDL CSG CVG -- -- -- -- -- fCLK DUTY Condition -- -- Digital input pins Digital input pins Digital input pins Digital input pins Digital output pins Between SGC and GND Between VDD and ground -- 255C In the temperature range -40 to +85C -- -- Values when an X1 external clock is input Min. 4.5 -40 0.8
x VDD
Typ. 5.0 -- -- -- -- -- -- -- --
3.579545
Max. 5.5 +85 VDD 0.2
x VDD
Unit V C V V ns ns pF F F MHz ppm ppm pF % %
0 -- -- -- 1 10 -- -100 -50 -- -- -0.1 40
50 50 100 -- -- -- +100 +50 90 -- +0.1 60
-- -- -- 16 -- --
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter Symbol IDD1 Power supply current IDD2 IDD3 IDD4 Input leak current High level output voltage Low level output voltage Input capacitance IIH IIL VOH VOL CIN Condition During operation (modem transmission/reception mode)*1 During operation (tone 1 mode)*1 During operation (tone 2, tone 3 modes)*1 During power down VI = VDD VI = 0 V IOH = -100 A IOL = 100 A -- Min. 0 0 0 0 -- -- VDD -0.1 0 -- Typ. 5.0 5.0 6.0 7.0 -- -- -- 0.05 5 Max. 10.0 10.0 11.0 100 2.0 0.5 VDD 0.1 -- Unit mA mA mA A A A V V pF
*1: See Table 3 for details of the modes. Analog Interface
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter Input resistance Output load resistance Output load capacitance Output impedance Symbol RIN RL1 RL2 RL3 CL ROX1 ROX2 VO1 Output DC voltage VO2 VS1 VS2 VS3 SW3 impedance Output current RSW3 ISGO LO-, LO+ Condition TI-, TI+, LI1-, LI1+, LI2- TIO, LI1O, LI2O TO (Output amplitude 1 Vpp or less) LO-, LO+ (differential outputs) Analog outputs TIO, LI1O, LI2O, TO LO-, LO+, SGO TIO, LI1O, LI2O, TO, LO-, LO+, SGC SGO 4 to 8 kHz 8 to 12 kHz (Differential outputs) 12 kHz to (4 kHz each) SW3 SGO pin (including via SW3) Min. 10 20 1.2 1.2 -- -- -- -- VDD/2 -0.1 -- -- -- -- -0.6 Typ. -- -- -- -- -- 10 10 VDD/2 VDD/2 -60 -80 -80 15 -- Max. -- -- -- -- 100 -- -- -- VDD/2 +0.1 -20 -40 -60 30 0.6 Unit M k k k pF V V dBm dBm dBm mA
Out-of-band spurious response
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AC Characteristics (DTMF Section)
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter Transmit level VDTTH Transmit signal level relative value Transmit signal frequency deviation Transmit signal distortion rate DTMF detection level DTMF non-detection level Detection frequency band Non-detection frequency band Level difference between two received frequencies Permissible received noise level Received dial tone elimination ratio Signal repetition period Input signal persistence duration Signal quiet duration Instantaneous break protection period Detection delay time Detection hold time SP delay time Signal repetition period Input signal persistence duration Signal quiet duration Instantaneous break protection period Detection delay time Detection hold time SP delay time ATT attenuation VDTDF fDDT THDDT VDETDT VREJDT fDETDT fREJDT VTWIST LOSSR6 VREJCP tc ts tl tp tba tbb tg td tsp tc ts tl tp tba tbb tg td tsp VATT Symbol VDTTL LO-, LO+_Differential *1 Condition Lower group tone Higher group tone Min. -7.0 -5.5 1 -1.5 -- -42 -- -- 3.8 -6 -- 37 120 49 -- 30 -- -- 24 24 0.2 60 35 -- 21 -- -- 12 15 0.2 -7.5 Typ. -4.5 -2.5 2 -- -- -- -- -- ---- -12 53 -- -- -- -- -- -- 41 28 0.6 -- -- -- -- -- -- 26 20 0.6 -6 Max. -3.0 -1.0 3 +1.5 -23 -6 -60 1.5 -- +6 -- -- -- -- 24 -- 0.4 10 49 35 1.0 -- -- 10 -- 0.4 3.0 37 27 1.0 -4.5 Unit dBm dBm dB % dB dBm dBm % % dB dB dB ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms ms dB
(Higher group tone) - (lower group tone) Relative to the nominal frequency (Harmonic waves) - (fundamental wave) For one frequency For one frequency Relative to the nominal frequency Relative to the nominal frequency (Higher group tone) - (lower group tone) (Noise level) - (tone level) 0.3 to 3.4 kHz 380 to 420 Hz
During the tone 1, tone 2, and loop back modes. See Figure 3 and Table 3 for details.
Detection Non-detection SP = 0 SP = 1
During the tone 3 mode. See Figure 3 and Table 3 for details.
Detection Non-detection SP = 0 SP = 1
Relative to the ATT = "0" reference
Note: 0 dBm = 0.775 Vrms *1: The value will be 6 dB smaller for pin LO+ or pin LO- alone.
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tba
tl ts DTMF signal
tc tp
tbb
tg DTMF receive data
td
SP
tsp
Figure 3
DTMF reception timing
Input signal persistence duration (detection) Normal reception is made when the input signal persistence duration is equal to ts or more. tI: Input signal persistence duration (non-detection) The input signal is ignored when the input signal persistence duration is less than tI, and the SP and DTMF receive data are not output. tp: Signal quiet duration The DTMF receive data and SP are reset if the input continues to be in the no-signal condition for a duration equal to tp or longer. Also, even if the receive data changes during DTMF signal reception, SP continues to be "1" and the DTMF receive data may remain in the initial value and may not change, if the signal quiet duration is less than tp (including when it changes without any instantaneous break). tba: Instantaneous break protection period 1 This is applicable to the period after the input signal has arrived and until the timing when SP becomes "1". In other words, SP and DTMF receive data are output normally even if a no-signal condition of a duration less than tba occurs. tbb: Instantaneous break protection period 2 This is applicable when SP is "1" (during output of the receive data). In other words, SP and the DTMF receive data are not reset even if a no-signal condition of a duration less than tbb occurs during signal reception. tc: For ensuring normal reception, make sure that the signal repetition period is equal to tc or more. tg: Detection delay time The DTMF receive data is output with a delay of tg relative to the appearance of the input signal. td: Detection hold time The output of SP or the DTMF receive data is stopped with a delay of td after the termination of the input signal. tsp: SP delay time SP is output after a delay of tsp relative to the output of the DTMF receive data. Therefore, latch the DTMF receive data when the rising edge of SP is detected.
ts:
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AC Characteristics (Modem Section)
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter Modem transmit level Transmit signal level relative value Transmit carrier frequency Receive signal level Carrier detection level Carrier detection hysteresis Carrier detection delay time Carrier detection hold time Demodulation bias distortion Symbol VAOM VDM fM fS VAI VON VOFF vHYS tCDD tCDH DBS Condition LO-, LO+ Differential (Mark signal) - (space signal) -- -- Level of LI1O and LI2O 1700 Hz -- OFF-30 dBm -30 dBmOFF 1200 bps, 1:1 pattern 5 23 -10 XD = 1 XD = 0 OFFON ONOFF Min. -6.0 -1.5 1292 2092 -51 -- -51 Typ. -4.0 0 1300 2100 -- -44.5 -46.5 2 10 28 -- Max. -2.0 +1.5 1308 2108 -6 -42 -- -- 15 34 +10 Unit dBm dB Hz Hz dBm dBm dBm dB ms ms %
Level of LI1O and LI2O
Note: RD is fixed at "1" when the carrier detector is OFF.
AC Characteristics (CLKO)
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter Symbol VCOH Output amplitude VCOL CL = 100 pF Condition Min. 0.9 x VDD 0 Typ. -- -- Max. VDD 0.1 x VDD Unit V V
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AC Characteristics (Call Progress Tone Section)
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter Transmit level Transmit frequency Distortion rate Detection level Non-detection level Detection frequency Non-detection frequency Detection persistence period Detection delay time Detection hold time Symbol VCPT fCPT THDCPT VDETCP VREJCP fDETCP frejCP tDETCP tREJCP tDELCP tHOLCP See Figure 4. Pin TO Condition Pin TO During 400 Hz output During 800 Hz output Pin TO 400 Hz, level of LI1O and LI2O 400 Hz, level of LI1O and LI2O -- -- Detection Non-detection Min. -21.5 380 780 -- -46 -- 360 510 -- 30 -- 10 10 Typ. -20.0 400 800 -- -- -- -- -- -- -- -- 17 17 Max. -18.5 420 820 -23 -6 -60 440 -- 300 -- 10 30 30 Unit dBm Hz Hz dB dBm dBm Hz Hz Hz ms ms ms ms
tREJCP
tDETCP
CPT input
tDELCP
tHOLCP
DETB
Figure 4
Call progress tone detection timing
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AC Characteristics (Processor Interface)
(VDD = 4.5 to 5.5 V, Ta = -40 to +85C) Parameter Write signal period Write signal width Read signal width Address data setup time Address data hold time Chip select setup time Chip select hold time Data setup time Data hold time Data output delay time Data output hold time Symbol PW TW TR TAW1 TAR1 TAW2 TAR2 TCW1 TCR1 TCW2 TCR2 TDW1 TDW2 tpd1 tpd2 See Figure 5. Condition Min. 2000 100 200 10 80 50 10 10 80 50 10 110 20 20 20 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- 60 40 Max. -- -- -- -- -- -- -- -- -- -- -- -- -- 150 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
A1, A0 TAW1
Address TAW2 TCW2 TAR1 TCR1
Address TAR2 TCR2
CSB
TCW1 WRB TW
TR
RDB
tpd2 TDW1 D0 to D3 TDW2 tpd1 Read data Write data
Figure 5
Processor interface timing
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FUNCTIONAL DESCRIPTION
Description of Processor Interface * List of Registers Table 1
A1 0 0 1 1 0 A0 0 1 0 1 0 R/W W R/W R/W R/W R
List of processor interface registers
D3 D2 PBG2 MODE2 SW2 CONT SW4 CONT PBR2 D1 PBG1 MODE1 CPTG ON MOD-DT ON PBR1 D0 PBG0 MODE0 CPT800 ATT PBR0
PBG3 SW1 CONT SW3 CONT SW5 CONT PBR3
* *
Data written into the registers other than the register [(A1, A0)=(0,0)] can be read out. Immediately after switching ON the power, use the LSI only after clearing the control registers using the power down mode.
* PBG3 to 0/PBR3 to 0 The registers PBG3 to 0 are used for setting the DTMF transmit data. The registers PBR3 to 0 are used for reading the DTMF receive data. The output frequency does not change even if the code is changed during transmission. Table 2 shows the data assignments. Table 2
D3 PBG3/ PBR3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 D2 PBG2/ PBR2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
DTMF transmit/receive data assignments
D1 D0 PBG0/ PBR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 0 # A B C D 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 CODE Lower group frequency (Hz) Higher group frequency (Hz)
PBG1/ PBR1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
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* MODE2 to MODE0 These registers are used for setting the mode. Table 3
The contents of setting are shown in Table 3. List of mode settings
Operation of different blocks MODE2 MODE1 MODE0 Mode name Modulator Demodulator DTMF DTMF CPT CPT section section transmission reception transmission reception Modem 0 0 0 O - - - O - transmission 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Modem reception Tone 1 (Note 1) Tone 2 (Note 1) Tone 3 (Note 1) Loop back (Note 2) Test Power down (Note 3) - - - - - - O O - - - O - - O O O - O O O O O O O O - - - O O -
LSI internal test - - - -
*[O]: Operating condition, [-]: Power down condition Note 1: Tone 1, 2, 3 modes The DTMF detection timing is different in the tone 1, 2, loop back modes from that in the tone 3 mode. In the tone 3 mode, the DTMF detection goes into the high speed detection mode. In this mode, since the detector can make incorrect detection due to voice signals or noise, avoid using the tone 3 mode if there is any margin available in the timing. Note 2: Loop back mode The modem loop back mode is initiated when SW5CONT is High and MOD-DT_ON is High. (The data input in XD is output from RD via the internal circuits.) The DTMF loop back mode is initiated when SW5CONT is Low and MOD-DT_ON is High. (The data set in PBG3 to PBG0 is latched at the rising edge of MOD-DT_ON, and is output at PBR3 to PBR0 via the internal circuits.) Note 3: Power down mode The conditions when the LSI is put in the power down mode are listed below. Each blocks: Stop operating and the internal circuits are reset. Analog output pins: Go to the high-impedance state DETB, RD, CLKO pins: High level SP, X2 pins: Low level Processor interface registers: Low level (excepting SW1CONT, MODE2, 1, 0)
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* SW1CONT This is the switch for selecting the DTMF reception input. 0: The input amplifier 1 is connected to the DTMF reception circuit. 1: The input amplifier 2 is connected to the DTMF reception circuit. * SW2CONT This is the switch for selecting the modem reception and CPT detection inputs. 0: The input amplifier 2 is connected to the modem reception circuit and the CPT detection circuit. 1: The input amplifier 3 is connected to the modem reception circuit and the CPT detection circuit. * SW3CONT This is the switch for external circuits, and can be used for connecting the termination, etc. 0: The switch goes into the OFF state. 1: The switch goes into the ON state. (The SWI pin and the SGO pin are connected together.) * SW4CONT This is the switch for selecting the signal (TO) of the output amplifier 1. 0: The CPT transmit output is connected to the output amplifier 1. 1: The output signal of SW2 is connected to the output amplifier 1. * SW5CONT This is the switch for selecting the signal (LO-, LO+) of the output amplifier 2. 0: The DTMF transmit output is connected to the output amplifier 2. 1: The modem transmit output is connected to the output amplifier 2. Set this to "1" during the modem transmit mode and set this to "0" during the DTMF transmit mode. * CPTG_ON This register is used for the ON/OFF control of call progress tone transmission. 0: CPT transmission becomes OFF and the signal is not output. 1: CPT transmission becomes ON and the signal is output. * CPT800 This selects the frequency of call progress tone transmission. 0: A 400 Hz signal is output. 1: An 800 Hz signal is output. * MOD-DT_ON This is used for the ON/OFF control of modem transmission or DTMF transmission. The transmission function is made ON/OFF of the block corresponding to the selected mode. 0: Modem transmission or DTMF transmission become OFF and the signal is not output. 1: Modem transmission or DTMF transmission become ON and the signal is output. In the DTMF transmission mode or in the DTMF loop back mode, PBG3 to 0 are latched at the rising edge of MOD-DT_ON. Set this to "0" during the modem reception mode and the tone 1 mode. * ATT This controls the attenuator of the DTMF transmission section. 0: No attenuator is inserted. The DTMF transmit signal is output as it is. 1: A -6 dB attenuator is inserted in the DTMF transmission section.
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APPLICATION CIRCUIT EXAMPLE
500 pF 30 k From terminal 30 k 500 pF From line 30 k 30 k
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
To terminal To line 10 F 1 F
VDD TIO TI- TI+ LI1O LI1- LI1+ SWI SGO LI2O LI2- TO LO+ LO- SGC GND
ML7020
SP DETB RD XD X1 X2 CLKO D3 D2 D1 D0 A1 A0 WRB RDB CSB
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
3.579545 MHz
MCU I/F
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PACKAGE DIMENSIONS
SSOP32-P-430-1.00-K
Mirror finish
5
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.60 TYP. 3/Dec. 5, 1996
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-todate. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd.
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